TNETX15AE datasheet(68/78 Pages) TI

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TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements (see Note 6 and Figure 21)

DRAM interface†

NO.

MIN

MAX

UNIT

tsu(DD)

Setup time, DD35–DD0 valid before OSCIN

↑

tsu(DWE)

Setup time, from DWE

↓ to OSCIN↑

tsu(DRAS)

Setup time, from DRAS

↓ to OSCIN↑

tsu(DCAS)

Setup time, from DCAS

↓ to OSCIN↑

th(DD)

Hold time, DD35–DD0 valid after OSCIN

↑

th(DWE)

Hold time, DWE low after OSCIN

↑

th(DRAS)

Hold time, DRAS low after OSCIN

↑

th(DCAS)

Hold time, DCAS low after OSCIN

↑

† DD35–DD0 data is available for two cycles

NOTE 6: The TNETX15AE listens on the DRAM interface to extract frame information. The TNETX15AE extracts information on only the write

cycles. The TNETX15AE does not output any signals to the DRAM interface. The only parameters that apply to the TNETX15AE on

this interface are delay times, with respect to OSCIN, that translate into the TNETX15AE setup times.

OSCIN

(Input)

Data

DWE

(Input)

DRAS

(Input)

DCAS

(Input)

DD35–DD0

(Input)

TNETX15AE Latches Here

Figure 21. DRAM Interface Timing

TNETX15AE 数据表(PDF) 68 Page - Texas Instruments

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