TNETX15AE datasheet(28/78 Pages) TI

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TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

interrupt masking register, intmask at 0x2A–0x2B (DIO)

The intmask register is used with the int register to select the type of interrupts that should be enabled to the

attached CPU. Bit definitions in the intmask register agree one-to-one with the bit definitions in the int register.

Only those fields with the bit set to 1 generate an interrupt to the CPU. Clearing the bit for a condition prevents

only the external terminal from moving to a logic 1 when the appropriate condition is true. The appropriate bit

in the interrupt register is always a 1 if the condition is true, and the bit has not been cleared by being read. This

BYTE 1

BYTE 0

BIT

NEW

NEWM

CHNG

CHNGM

SECVIO

SECVIOM

AGE

AGEM

INT

Reserved

STAT

FULL

Initial values after reset

BIT

NAME

FUNCTION

NEW

New-node interrupt mask. When NEW is set, a new-node interrupt is posted if the NEW bit in the int register is set.

NEWM

Missed-new-node interrupt mask. When NEWM is set, a missed new-node interrupt is posted if the NEWM bit in the int

CHNG

Node-port change interrupt mask. When CHNG is set, a node-port change interrupt is posted if the CHNG bit in the int

CHNGM

Missed-node-port change interrupt mask. When CHNGM is set, a missed-node-port interrupt is posted if the CHNGM

bit in the int register is set.

SECVIO

Security-violation interrupt mask. When SECVIO is set, a security-violation interrupt is posted if the SECVIO bit in the

int register is set.

SECVIOM

Missed-security-violation interrupt mask. When SECVIOM is set, a missed-security-violation interrupt is posted if the

SECVIOM bit in the int register is set.

AGE

Age-out interrupt mask. When AGE is set, an age-out interrupt is posted if the AGE bit in the int register is set.

AGEM

Missed-age-out interrupt mask. When AGEM is set, a missed age-out interrupt is posted if the AGEM bit in the int register

is set.

INT

Test interrupt mask. When INT is set, a test interrupt is posted if the INT bit in the int register is set.

6–2

Reserved

Writes to this location are ignored and read as 0.

STAT

Statistics overflow interrupt mask. When STAT is set, a statistics interrupt is posted if the STATS bit in the int register

is set.

FULL

SRAM full interrupt mask. When FULL is set, a memory-full interrupt is posted if the FULL bit in the int register is set.

TNETX15AE 数据表(PDF) 28 Page - Texas Instruments

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