TNETX15AE datasheet(43/78 Pages) TI

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TNETX15AE

ADDRESS-LOOKUP DEVICE

SPWS041A – AUGUST 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

lookup table SRAM allocation (continued)

Table 0 (Root)

Table 1

Table 2

Table 3

Table 4

Table 5

Table 6

Table 7

Table 8

Table Level 9

is 8 Address Descriptor Blocks

Bits 47–43

Bits 42–38

Bits 37–33

Bits 32–28

Bits 27–23

Bits 22–18

Bits 17–33

Bits 12–8

Bits 7–3

Bits 2–0

Figure 10. Address Tables

The last level decodes only bits 2–0 of the address, therefore, only eight unique locations are required. Since

tables are allocated 32 words at a time, the last table is divided into eight four-word units. The lower eight bits

of each word hold one byte of the address descriptor block as shown in Figure 11.

BYTE 1

BYTE 2

BYTE 3

BYTE 4

Flags/port code

Reserved

MSG age stamp

LSB age stamp

Figure 11. Address Descriptor Block Format

Since only the first byte of the address descriptor block is required to make a forwarding decision, an address

lookup requires 40 ns to access each of 10 levels for a total 400-ns lookup time plus an internal setup cycle.

The total time required (400 ns + 20 ns) gives some margin to generate the EAM code in time for the

TNETX3150/TNETX3150A/TNETX3100.

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