AD6650SLASHPCB datasheet(29/45 Pages) AD

29 / 45 page

AD6650

Rev. A | Page 28 of 44

–35

–75

OFFSET FREQUENCY (kHz)

1000

100

–40

–45

–50

–55

–60

–65

–70

Figure 40. Output Spurious vs. Power Supply Ripple (AIN = 199 MHz)

An additional parameter that strongly impacts the PSRR is the

sensitivity to the AVDD voltage level. A plot of spur level versus

AVDD is shown below in Figure 41. Note that this plot also has

the spur level referenced to 1mV rms supply ripple and is

referred to the LO. Thus, this plot shows a transfer function

rather than an absolute value. The spurious level can be

extrapolated to any supply ripple level from this plot using

Equation 21.

–20

–50

2.95

3.60

AVDD (V)

–23

–26

–29

–32

–35

–38

–41

–44

–47

3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 3.55

Figure 41. Output Spurious vs. Power Supply Ripple (AIN = 199 MHz)

The AD6650 has separate digital and analog power supply pins.

The analog supplies are denoted AVDD, and the digital supply

pins are denoted DVDD. Although analog and digital supplies

can be tied together, best performance is achieved when the

supplies are separate because the fast digital output swings can

couple switching current back into the analog supplies. Note

that AVDD and DVDD must be held between 3.0 V and 3.45 V.

DIGITAL OUTPUTS

It is recommended that the digital outputs drive a series resistor

(for example, 100 Ω). To minimize capacitive loading, the

number of gates on each output pin should be limited. The

series resistors should be placed as close to the AD6650 as

possible to limit the amount of current that can flow into the

output stage. These switching currents are confined between

ground and the DVDD pin. Also, note that excessive capacitive

loading increases output timing and can invalidate timing

specifications.

GROUNDING

For optimum performance, it is highly recommended to use a

split ground between the analog and digital grounds. AGND

should be connected to the analog ground of the RF board, and

DGND should be connected to the digital ground of the RF board.

To minimize the potential for noise coupling, it is highly

recommended to place multiple ground return traces and vias

so that the digital output currents do not flow back toward the

analog front end, but instead are routed quickly away from the

AD6650. This can be accomplished by simply placing

substantial ground connections directly back to the supply at a

point between the analog front end and the digital outputs.

Judicious use of ceramic chip capacitors between the power

supply and ground planes also helps suppress digital noise. The

layout should incorporate enough bulk capacitance to supply

the peak current requirements during switching periods.

LAYOUT INFORMATION

A multilayer board should be utilized to achieve optimal results.

It is highly recommended to use high quality ceramic chip

capacitors to decouple each supply pin to ground directly at the

device. The pin arrangement of the AD6650 facilitates ease of

use in the implementation of high frequency, high resolution

design practices. All of the digital outputs are on the opposite

side of the package from the analog inputs for isolation purposes.

Care should be taken when routing the digital output traces. To

prevent coupling through the digital outputs into the analog

portion of the AD6650, minimal capacitive loading should be

placed on these outputs.

The layout of the encode circuit is equally critical. Any noise

received on this circuitry results in corruption in the digitization

process and lower overall performance. The encode clock must

be isolated from the digital outputs and the analog inputs.

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