AD6650SLASHPCB datasheet(21/45 Pages) AD

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AD6650

Rev. A | Page 20 of 44

FREQUENCY (MHz)

–10

–20

–40

–50

–30

–60

–70

–90

–100

–110

–80

–120

–1.98

–1.46

–0.94

0 17

–0.43

1.13

1.65

0.61

2.17

AD6650 DIGITAL

COMPOSITE

RESPONSE

CIC4 RESPONSE

IIR FILTER

RESPONSE

Figure 26. Composite Digital Response with 8× Rate

FINE DC CORRECTION

The fine dc correction block in the AD6650 lies between the

RCF and serial output port. While the coarse dc correction

block at the front of the channel is included to provide a one-

time correction at startup or at rare intervals when commanded

by the user, the fine dc correction block is intended to run

continuously and track any changes in the dc offsets of the

analog front end. To achieve this efficiently under varying

signal conditions, this dc estimation process is adaptive.

Adaptive DC Correction Filter

In typical applications where dc offsets are to be corrected, a

high-pass filter (HPF) is used to remove the dc and some small

percentage of the input signal power. This approach is

straightforward and works well when the input signal has a

relatively constant power or when the bandwidth of the HPF is

extremely small (in the μHz or nHz range) and the dc content

does not vary. In general, the more the input signal power can

vary, the narrower the bandwidth of the high-pass filter must be

to avoid low frequency transients in the filter that are larger

than the smallest expected signals. A fundamental trade-off

exists because if the high-pass filter has a very low bandwidth, it

can only track very slow changes (over hours, days, or weeks) in

the dc offsets of the device. On the other hand, if it has a higher

bandwidth, it may not be able to estimate the dc properly in the

presence of a large baseband signal.

Given the assumption that the signal of interest is uniformly

distributed across frequency, the processing gain equation can

be used to provide a starting point for system optimization.

Enough processing gain must be guaranteed for the dc estimate

to be valid for a minimum signal case. This is typically 20 dB to

30 dB but depends on the baseband signal processing of a

particular system. For GSM/EDGE, which is distributed over

~100 kHz single sideband (SSB), this implies that the HPF

bandwidth must be between 100 Hz to 1 kHz SSB. For every

6 dB that the signal power increases, 6 dB more processing gain

is required; therefore, the HPF bandwidth needs to decrease by

a factor of 4 or more.

(14)

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

HPF

log

(14)

where:

fBW is the channel filter bandwidth.

fHPF is the HPF bandwidth.

In the case of GSM, a simple HPF is not well suited to this

problem because the signal power can vary 50 dB or more from

time slot to time slot and has a total dynamic range of 91 dB or

more. A large time slot would excite the impulse response of the

HPF, possibly resulting in a peak occurring later when a small

time slot is present. To provide a more optimal dc correction,

the AD6650 adaptively adjusts the bandwidth of the HPF based

on the signal power. As the signal level decreases, the HPF

bandwidth increases. Conversely, as the signal level increases,

the HPF bandwidth decreases.

The AD6650 implements this high-pass filter in the form of an

accumulator that integrates a number of samples of the output

of the RCF and produces an estimate after the samples are

accumulated. The estimated dc is then removed from the signal

path by a simple subtraction. The subtraction is clamped to

avoid overflow problems. The HPF bandwidth is varied by

changing the integration time (equivalent to a SYNC 1 filter

decimation of the integrator). The integration time is varied based

on the output of a peak detector circuit according to the process

described in the Peak Detector DC Correction Ranging section.

PEAK DETECTOR DC CORRECTION RANGING

The peak detector of the AD6650 always looks at the maximum

signal power present in the I or Q data path. The I and Q paths

are treated totally independently in the dc correction circuitry

because the analog paths are not guaranteed to match. The first

sample that arrives is rectified and preloaded into the peak

detector. A control counter is set to the minimum period

control register setting. On every input sample, the peak

detector determines if the new sample is larger than the

currently held sample, and if so, the peak detector is updated.

The contents of the peak detector are then examined. If they are

below the lower threshold, the control counter counts down and

when it reaches 0, it updates the dc estimate, resets the dc

accumulator, and reloads the peak detector with the newest

input sample magnitude. If the peak detector value is above the

upper threshold of the dc correction, the estimate currently

being calculated is discarded. When the signal drops below the

upper threshold, the calculation of a new dc estimate begins.

The current estimate is held, so the last known dc content

continues to be removed.

The AI, AQ, BI, and BQ paths of the AD6650 are each treated

independently in the dc correction circuitry because the analog

paths are not guaranteed to match, and separate dc estimates

need to be kept for each. Separate peak detectors, dc estimate

accumulators, dc estimate subtractors, and control counters are

implemented for each of these paths.

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