AD6650SLASHPCB datasheet(13/45 Pages) AD

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AD6650

Rev. A | Page 12 of 44

Mnemonic

Type

Description

No. of Pins

DTACK (RDY)

Output

Active Low Data Acknowledge (Microport Status Bit). Open-drain output, requires

external pull-up resistor of 1 kΩ.

R/W (WR)

Input

Read Write (Active Low Write).

MODE [2:0]

Input

Selects Control Port Mode.

JTAG

TRST

Input

Test Reset Pin.

TCLK

Input

Test Clock Input.

TMS

Input

Test Mode Select Input.

TDO

Output

Test Data Output. Three-stated when JTAG is in reset.

TDI

Input

Test Data input.

ANALOG INPUTS

AIN

Input

Main Analog Input.

AIN

Input

Complement of AIN. Differential analog input.

BIN

Input

Diversity Analog Input.

BIN

Input

Complement of BIN. Differential analog input.

PLL INPUTS

CPOUT

Output

Charge-Pump Output.

Input

Loop Filter.

VLDO

Output

Compensation for Internal Low Dropout Regulator. Bypass to ground with a 220

nF chip capacitor.

REFT

Output

Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39

for recommended connection.

REFB

Output

Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39

for recommended connection.

VREF

Output

Internal ADC Voltage Reference. Bypass to ground with capacitors. See Figure 39

for recommended connection.

REFGND

Ground

ADC Ground Reference. See Figure 39 for recommended connection.

CLOCK INPUTS

CLK

Input

Encode Input. Conversion initiated on rising edge.

CLK

Input

Complement of Encode.

DNC

Do Not Connect.

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