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AD6650/PCB 数据表(PDF) 32 Page - Analog Devices |
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AD6650/PCB 数据表(HTML) 32 Page - Analog Devices |
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32 / 45 page  AD6650 Rev. A | Page 31 of 44 Table 14. Microport Instructions Instruction Description 0xxx All chips obtain access. 1000 All chips with Chip_ID [1:0] = x0 obtain access.1 1001 All chips with Chip_ID [1:0] = x1 obtain access.1 1100 All chips with Chip_ID [1:0] = 00 obtain access.1 1101 All chips with Chip_ID [1:0] = 01 obtain access.1 1110 All chips with Chip_ID [1:0] = 10 obtain access.1 1111 All chips with Chip_ID [1:0] = 11 obtain access.1 1 Bits A[9:8] control which channel is decoded for the access. For SF2, Bit 0 prompts the startup block to run the start hold- off counter from the value programmed in the start holdoff counter control register and to issue a sync when this task is complete. Bit 4 to Bit 6 are used to enable syncs to individual blocks in the channels. DATA ADDRESS REGISTERS External Addresses [2:0] form Data Register DR2, Data Register DR1, and Data Register DR0, respectively. All internal data- words have widths that are less than or equal to 22 bits. Access to DR0 triggers an internal access to the AD6650 based on the address indicated in ACR and CAR. Therefore, during writes to the internal registers, DR0 must be written last. At this point, data is transferred to the internal memory location indicated in A[9:0]. Reads are performed in the reverse sequence. Once the address is set, DR0 must be the first data register read to initiate an internal access. DR2 is only six bits wide. Data written to the upper two bits of this register is ignored. Likewise, reading from this register produces only 6 LSBs. WRITE SEQUENCING Writing to an internal location is achieved by first writing the upper two bits of the address into Bit 1 and Bit 0 of the ACR (these bits should be set low). Bits[5:2] can be set to select the chips for access as indicated above. The CAR is then written with the lower eight bits of the internal address (it does not matter if the CAR is written to before the ACR, as long as both are written to before the internal access). DR2 and DR1 must be written first because the write to Data Register DR0 triggers the internal access. DR0 must always be the last register written to initiate the internal write. READ SEQUENCING Reading from the microport is accomplished in the same manner. The internal address is set up the same way as it is for a write. A read from DR0 activates the internal read; therefore, DR0 must be read first to initiate an internal read followed by reads from DR1 and DR2. READ/WRITE CHAINING The microport of the AD6650 allows multiple accesses while CS is held low (CS can be tied permanently low if the microport is not shared with additional devices). The user can access multiple locations by pulsing the WR or RD line and changing the contents of the external 3-bit address bus. Access to the external registers listed in Table 13 is accomplished in one of two modes using the CS, RD, WR, and MODE inputs. The access modes are INM mode and MNM mode. These modes are controlled by the MODE input (MODE = 0 for INM, MODE = 1 for MNM). CS, RD, and WR control the access type for each mode. PROGRAMMING MODES The AD6650 can be programmed using several different modes. These modes include two microport modes, INM mode and MNM mode. The programming mode is selected by setting the MODE pins. Table 15 identifies how to set the MODE pins to select the desired programming mode. Table 15. Programming Modes MODE [2:0] Description 000 Microport Intel nonmultiplexed mode 001 Microport Motorola nonmultiplexed mode 010 Reserved 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Reserved Intel Nonmultiplexed Mode (INM) Setting the mode word bits to 000 places the AD6650 in INM mode. The access is controlled by the user with the CS, RD (DS), and WR (R/W) inputs. The RDY (DTACK) signal is produced by the microport to communicate to the user that an access has been completed. RDY (DTACK) goes low at the start of the access and is released when the internal cycle is complete. See Figure 10 and Figure 11 for INM mode read and write timing. Motorola Nonmultiplexed Mode (MNM) Setting the mode word bits to 001 places the AD6650 in MNM mode. The access type is controlled by the user with the CS, DS (RD), and R/W (WR) inputs. The DTACK (RDY) signal is generated by the microport to signal the user that an access has been completed. DTACK (RDY) goes low when an internal access is complete and returns high after DS (RD) is deasserted. See Figure 12 and Figure 13 for MNM mode read and write timing. |
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