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AD6650/PCB 数据表(PDF) 39 Page - Analog Devices

部件名 AD6650/PCB
功能描述  GSM/EDGE Narrow-Band Receiver
PDF  45 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6650/PCB 数据表(HTML) 39 Page - Analog Devices

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AD6650
Rev. A | Page 38 of 44
Reg.
(Hex)
Mnemonic
Bit
Width
Description
Additional Information
Code
Taps
1B
RCF Taps (NTaps − 1)
6
1 to 48.
0
1
1
2
.
.
.
.
46
47
47
48
Code
Scale Factor
1C
RCF Scale
2
0
−18 dB
1
−12 dB
2
−6 dB
0, −6 dB, −12 dB, and −18 dB gain adjust to
prevent coefficients from clipping the MAC.
3
0 dB
1D
BIST for A-I
24
16-bit data available, I/DATA_I.
1E
BIST for A-Q
24
16-bit data available, Q/DATA_Q.
1F
BIST for B-I
24
16-bit data available, I/DATA_I.
20
BIST for B-Q
24
16-bit data available, Q/DATA_Q.
21
Serial Control
9
Power-up value is 9’bxxxxx0xxx for Bit 3 to
make it a serial slave.
8: Fine DCC Data to BIST
1
Data is available through the I/Q BIST
registers when Bit 8 is high.
Code
Results
1
Port B data serial output select.
0
Use SDO0 for
B data
7: B Data Serial Ouput
Select
1
Use SDO1 for
B data
6 to 5: I_SDFS Control
2
Serial port control functions.
0
AI pulse
1
AI, BI pulses
2
AI, AQ, BI,
BQ pulses
3
High for
SDO0 valid
4: SOWL
1
Serial output word length.
0
16-bit words
1
24-bit words
3: SBM
1
Serial bus master.
0
Serial slave
1
Serial bus
master
2 to 0: SDIV [2:0]
3
Serial divider.
0
Divide-by-1
.
.
.
.
7
Divide-by-8
22
AutoCalibration Control
4
New calibration sequence control registers.
Power-up value is 4’b0000.
3: Reserved
1
Reserved.
Must be written 0
2: Reserved
1
Reserved.
Must be written 1
Code
Results
1
0
Power down
DACs
1: DAC Power-Down
Disable
Power down VGA DACs during the power-up
sequence to calibrate the dc offset.
1
DACs on
0: Enable
1
Autocalibration enable.
0
Disabled
1
Enabled
23 to
3F
Reserved
40 to
6F
Coefficient Memory
Common coefficients for Channel A and
Channel B.
48 × 20 bit RAM
70 to
FF
Reserved



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