AD6650SLASHPCB datasheet(19/45 Pages) AD

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AD6650

Rev. A | Page 18 of 44

INFINITE IMPULSE RESPONSE (IIR) FILTER

The IIR filter of the AD6650 is a seventh-order low-pass filter

with an infinite impulse response. This filter cannot be bypassed

and always performs a decimation of 2. As can be seen from the

Z-transform, the IIR filter has a gain of −6.02 dB to accommodate

signal peaking within the structure. It is designed to be free of

limit cycles and is unconditionally stable. The IIR filter is

described by the Z-transform and coefficients shown in the

following equation:

() ()

() 2

IIR

(9)

where:

n0 = 0.046227

n1 = 0.278961

n2 = 0.76021

n3 = 1.208472

d0 = 0

d1 = 0.12895

d2 = 0

d3 = 0.254698

d4 = 0

d5 = 1.026276

d6 = 0

d7 = 1

Figure 23 shows the magnitude response of the IIR filter in a

typical GSM/EDGE case where the ADCs are sampling at

26 MHz and the CIC filter is decimating by 12 to generate a

2.16 MHz (8× symbol rate) input rate to the IIR.

–30

–40

–50

–10

–20

–60

–70

–80

–100

–110

–90

–120

FREQUENCY (MHz)

IIR RESPONSE

Figure 23. IIR Frequency Response

Figure 24 shows the phase response of the IIR filter over the

range of ±100 kHz after a time delay during which ~13.449 input

samples of the filter have been removed. The input rate is the

same 2.16 MHz from the above GSM/EDGE configuration.

Examining the plot shows that the IIR filter is not exactly phase

linear. (Linear phase would be flat after the time delay has been

removed). It can be seen, however, that the phase response over

the band of interest is essentially perfect. From −100 kHz to

+100 kHz, the phase distortion is ~0.056° rms. This phase

response is several orders of magnitude below the analog LO

and analog filter phase distortions.

CHANNEL BW (kHz)

0.001

6 × 10–4

2 × 10–4

–2 × 10–4

–6 × 10–4

–0.001

–100

–50

100

IIR PHASE RESPONSE

Figure 24. IIR Phase Response

RAM COEFFICIENT FILTER

The final signal processing stage is a sum-of-products decimating

filter with programmable coefficients (see Figure 25). The I-RAM

and Q-RAM data memories store the most recent complex

samples from the IIR filter with 23-bit resolution. The number

of samples stored in these memories is equal to the coefficient

length (Ntaps), up to 48 taps. The coefficient memory, CMEM,

stores up to 48 coefficients with 20-bit resolution. On every

CLK (up to 52 MHz) cycle, one tap for I and one tap for Q are

calculated using the same coefficients. The RCF output consists

of 16-bit or 24-bit data.

48 × 23

I-RAM

COARSE

SCALE

RND

WORD

I IN

48 × 20

C-RAM

48 × 23

Q-RAM

Q IN

Figure 25. Block Diagram of the RCF

RCF Decimation Register

Each RCF channel can decimate the data rate by a factor of 1 to

8. The decimation register is a 3-bit register. The RCF decimation is

stored in Address 0x18 in the form of MRCF − 1. The input rate

to the RCF is fSAMPIIR.

RCF Decimation Phase Register

The AD6650 uses the value stored in this register to preload the

RCF counter. Therefore, instead of starting from 0, the counter

is loaded with this value, thus creating a time offset in the

output data. This data is stored in Address 0x19 as a 3-bit

number. Time delays can be achieved in even units of the RCF

input rate, which is typically ¼ of the symbol time for GSM.

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