AD6650SLASHPCB datasheet(35/45 Pages) AD

35 / 45 page

AD6650

Rev. A | Page 34 of 44

Reg.

(Hex)

Mnemonic

Bit

Width

Description

Additional Information

DC Correction Control

Fine DCC control registers.

Power-up value is

20’b00000000000000000000

Code

Level (dBFS)

0 dBFS

−0.75 dBFS

−1.5 dBFS

126

−94.5 dBFS

19 to 13: Upper

Threshold

Fine DCC upper threshold. No new dc

estimation is made if the signal is above the

upper threshold.

127

−95.25 dBFS

0 dBFS

−6.02 dBFS

−12.04 dBFS

−132.44 dBFS

12 to 8: Lower Threshold

Fine DCC lower threshold. The maximum

range for the lower limit is 0 dBFS to

138.46 dBFS.

−138.46 dBFS

Code

Integration

Time

Fine DCC integration period.

21 × TS

22 × TS

23 × TS

230 × TS

231 × TS

7 to 3: Minimum Period

TS = sample

period

Code

Result

2: Bypass

Fine DCC bypass.

Update DCC

estimate

Keep old

estimate

1: Interpolate

Disabled

Enabled

Fine DCC interpolator reduces discontinuity

between the current dc estimate and the

new estimate.

0: Freeze

Disabled

Fine DCC freeze is used to hold the current

dc estimate.

Enabled

AGC Control 0

AGC Control Settings.

Code

Result

3: Force VGA Gain

Disabled

Force the VGA gain to a specific value. This

control line overrides the slow loop, fast

decay loop, and fast attack loop when

enabled.

Enable forced

gain mode

2: FD_Enable

Fast decay loop enable.

Disabled

Enable fast

decay loop

Code

Result

1: FA_Enable

Fast attack loop enable.

Disabled

Enable fast

attack loop

0: Reserved

Reserved.

N/A

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AD6650/PCB 数据表(PDF) 35 Page - Analog Devices

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