AD6650SLASHPCB datasheet(42/45 Pages) AD

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AD6650

Rev. A | Page 41 of 44

and constantly corrected. This is useful for debugging and for

use when the dc estimate can be performed at discrete

predefined times.

Even though the upper threshold register can vary between 0

and 15 and the Min_period register can vary between 1 and 31,

only certain combinations of the two are valid. This is because

the growth is restricted to 34 bits. Equation 2

3 can be used to

determine if a combination of values is valid. If C < 0, the

combination is invalid; otherwise, the combination is valid.

C = 34 − (2 × (16 − Upper Threshold) + Min_period)

0x0C: AGC Control 0 [3:0]

Bit 3

The force VGA gain control register allows the user to force the

VGA gain to a specific value. This control line overrides the slow

loop, fast decay loop, and fast attack loop when enabled. By setting

this bit low, the force VGA gain control is disabled. By setting

this bit high, the force VGA gain control is enabled. For normal

operation, this bit should be disabled.

Bit 2

By setting this bit high, the fast decay loop is enabled; by setting

this bit low, the fast decay loop is disabled. It is recommended

that the fast decay loop be enabled for normal operation. For a

description of the fast decay functionality, see the AGC

Loop/Relinearization section.

Bit 1

By setting this bit high, the fast attack loop is enabled; by setting

this bit low, the fast attack loop is disabled. It is recommended

that the fast decay loop be enabled for normal operation. For a

description of the fast attack functionality, see the AGC

Loop/Relinearization section.

Bit 0

This bit is reserved and should be written low.

0x0D: AGC Control 1 [8:0]

If the force VGA bit is enabled in AGC Control Register 0

(Bit 3 = 1), this register controls the gain setting for the VGA.

The gain is controlled in 0.094 dB steps with a maximum gain

of 36 dB. Code 0 corresponds to 0 dB gain or minimum gain,

whereas Code 383 corresponds to 36 dB gain or maximum gain.

0x0E: AGC Control 2 [15:0]

The AGC Control 2 register is a 16-bit register that sets the

amount of hysteresis used in the AGC loop and sets the

requested level for the AGC loop.

Bit 15 to Bit 8

These upper bits set the hysteresis level in 0.094 dB steps. Code 0

corresponds to 0 dB of hysteresis, and Code 255 corresponds to

±23.97 dB of hysteresis.

Bit 7 to Bit 0

These lower eight bits set the requested level for the AGC slow

loop. Setting the code to 0 sets the requested level to +4 dBm,

which corresponds to the full-scale input of the AD6650.

Setting the code to 255 sets the requested level to −19.97 dBm.

0x0F: AGC Control 3 [10:0]

Bit 10 to Bit 8

This 3-bit register sets the loop gain exponent

for the slow loop of the AD6650 AGC. The values can range

from 0 to 7. The equation for the loop gain is noted in the AGC

Loop/Relinearization section.

Bit 7 to Bit 6

These two bits are reserved and should be written low.

Bit 5 to Bit 0

This 6-bit register represents the loop gain mantissa for the slow

loop of the AD6650 AGC. The values for this register range from 0

to 63. The equation for the loop gain is noted in the AGC

Loop/Relinearization section.

0x10: AGC Control 4 [12:0]

Bit 12 to Bit 10

This 3-bit register is used to set the fast decay step size. The gain

continues to increase until it has reached the fast decay

threshold or until the maximum gain has been reached.

Bit 9 to Bit 8

This 2-bit register sets the threshold for the fast attack AGC

loop. When the desired signal reaches this threshold, the gain is

reduced by the FA_Step for FA_Count number of clock cycles.

Bit 7 to Bit 4

The fast attack loop steps the gain down by FA_Step for

FA_Count number of clock cycles.

Bit 3 to Bit 0

The FA_Step register determines how large a step to take once

the fast attack threshold has been reached. This value is

expressed in decibels.

0x11: AGC Control 5 [15:0]

Bit 15 to Bit 8

This 8-bit register sets the signal plus blocker peak detector

period for the AGC slow loop. It can be set from 0 to 255 samples.

Bit 7 to Bit 0

Reserved and must be written 00000000.

0x12: Reserved [6:0]

This register is reserved and must be written 0000000.

0x13: AGC Control 7 [8:0]

This 9-bit register is used to set the threshold for the fast decay

signal plus blocker. Values can range from 0 dBFS to −48 dBFS.

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