AD6650SLASHPCB datasheet(26/45 Pages) AD

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AD6650

Rev. A | Page 25 of 44

SDO

SDO is the serial data output. Serial output data is shifted on

the rising edge of SCLK. On the next SCLK rising edge after an

SDFS, the MSB of the I data from the channel is shifted.

On every subsequent SCLK edge, a new piece of data is shifted

out on the SDO pin until the last bit of data is shifted out. The

last bit of data shifted is the LSB of the Q data from the channel.

SDO is three-stated when the serial port is outside its time slot.

This allows the AD6650 to share the SDIN of a DSP with other

AD6650s or other devices.

SDFS

SDFS is the serial data frame sync signal. SDFS is configured as

an output. SDFS is sampled on the falling edge of SCLK. When

SBM is sampled high, the chip functions as a serial bus master.

In this mode, the AD6650 is responsible for generating serial

control data. Four modes of that operation are set via Channel

Address 0x21, Bit 6 to Bit 5.

Serial Word Length

Bit 4 of Address 0x21 determines the length of the serial word

(I or Q). If this bit is set to 0, each word is 16 bits wide (16 bits

for I and 16 bits for Q). If this bit is set to 1, the serial words are

24 bits wide.

SDFS Modes

As mentioned in the Serial Data Frame Sync section, there are

three modes of operation.

Setting Bit 7 of Address 0x21 high indicates that Input Channel A

data is output on SDO0 and Input Channel B data is output on

SDO1. In this condition, there are three modes of operation.

(There are technically four modes, but Mode 0 and Mode 1 are

the same).

•

Mode 0 and Mode 1 (Address 0x21, Bits[6 :5] = 00;

Bit[7] = 1): The SDFS is valid for one complete clock cycle

prior to the data shift. This single pulse is valid for Output

Channel SDO0 and Output Channel SDO1. On the next

clock cycle, the AD6650 begins shifting out the digitally

processed data stream. Depending on the bit precision of

the serial configuration, either 16 bits or 24 bits of I data

are shifted out, followed by 16 bits or 24 bits of Q data.

•

Mode 2 (Address 0x21

, Bits[6:5] = 10; Bit[7] = 1): Because

both SDO0 and SDO1 are used, SDFS pulses high one

clock cycle prior to I data and also pulses high one clock

cycle prior to Q data for each corresponding input channel. In

this mode, there are two SFDS pulses per each output channel.

•

Mode 3 (Address 0x21

, Bits[6:5] = 11; Bit[7] = 1): The SDFS

is high while valid bits are being shifted. On SDO0, SDFS

remains high for 16 bits or 24 bits of I data, followed by

16 bits or 24 bits of Q data corresponding to Input Channel A.

For SDO1, SDFS remains high for 16 bits or 24 bits of I data,

followed by 16 bits or 24 bits of Q data corresponding to

Input Channel B. The SDFS bit goes high one complete

clock cycle before the first bit is shifted out of the AD6650.

AD6650/PCB 数据表(PDF) 26 Page - Analog Devices

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