AD6650SLASHPCB datasheet(43/45 Pages) AD

43 / 45 page

AD6650

Rev. A | Page 42 of 44

The peak detector for this threshold monitors the desired signal

and blocker peaks at the ADC output.

0x14: Start Holdoff Counter [15:0]

The start holdoff counter is loaded with the value written to this

address when a sync is initiated. It can be initiated by either a

Soft_SYNC or Pin_SYNC. The counter begins decrementing,

and when it reaches a value of 1, the channel exits sleep mode

and begins processing data. If this register is written 1, the start

occurs immediately when the SYNC comes into the channel. If

it is written 0, no SYNC occurs.

0x15: CIC4 Decimation Minus One (MCIC4 − 1) [4:0]

This register is used to set the decimation in the CIC4 filter. The

value written to this register is the decimation minus one. The

value of this register should be 12 or greater because the CIC

and IIR have maximum rates of 26 MHz/12. Although this is a

5-bit register, the decimation is usually limited to between 12

and 32. Decimations higher than 32 require more scaling than

the CIC4’s capability.

0x16: CIC4 Scale [3:0]

The CIC4 scale factor is used to compensate for the growth of

the CIC4 filter. See the Fourth-Order Cascaded Integrator

Comb Filter (CIC4) section for details.

0x17: IIR Control Register [1]

Address 0x17 is the IIR control register. When this bit is set to 0,

the sync mask is disabled. In this mode, after a SYNC is issued

to the AD6650, the IIR data path is not cleared. If the sync mask

is enabled, the bit is set to 1, and the data path is cleared of its

contents and starts accumulating new data on the first valid

clock after a Soft_SYNC or Pin_SYNC is issued.

0x18: RCF Decimation Register Minus One (MRCF − 1) [2:0]

This register is used to set the decimation of the RCF stage. The

value written is the decimation minus one. This is a 3-bit

0x19: RCF Decimation Phase (PRCF) [2:0]

This register allows any one of the MRCF phases of the filter to

be used and can be adjusted dynamically. Each time a filter is

started, this phase is updated. When a channel is synchronized,

it retains the phase setting selected. This can be used as part of a

timing recovery loop with an external processor or can allow

multiple RCFs to work together while using a single RCF pair.

See the RAM Coefficient Filter section for more details.

0x1A: RCF Coefficient Offset (CORCF) [5:0]

This register is used to specify which section of the 256-word

coefficient memory is used for a filter. It can be used to select

among multiple filters that are loaded into memory and

referenced by this pointer. This register is shadowed and the

filter pointer is updated every time a new filter is started. This

allows the coefficient offset to be written even while a filter is

being computed without disturbing operation. The next sample

that comes out of the RCF will be with the new filter.

0x1B: RCF Taps Minus One (NTAPS − 1) [5:0]

The number of taps for the RCF filter minus one is written to

this register.

0x1C: RCF Scale Register [1:0]

This 2-bit register represents the output scale factor of the RCF.

This register is used to scale the output data between 0 dB and

−18 dB in 6 dB steps.

0x1D to 0x20: BIST Register [23:0]

These four registers allow the complete digital functionality of

the I and Q data path in the A and B channels to be tested in the

system. See the User-Configurable Built-In Self-Test (BIST)

section for more details.

0x21: Serial Control Register [8:0]

This register controls the serial port of the AD6650 and

determines the output format.

Bit 8

Fine DCC data to BIST.

Bit 7

If this bit is enabled (set high), Channel B data is output on

Serial Data Output 1 (SDO1).

Bit 6 to Bit 5

Choose the serial data frame sync (SDFS) mode. See the Serial

Data Frame Sync section for a full description of each mode. The

following bits select the corresponding mode.

Table 25. Serial Port Control Functions

Bits

Description

High for SDO0 valid

AI, AQ, BI, BQ pulses

AI, BI pulses

AI pulse

Bit 4

By setting this bit low, the output data stream is 16-bit I and 16-bit

Q data-words for both the A and B channels. By setting this bit

high, the output data stream is 24-bit I and 24-bit Q data words

for both the A and B chan nels. To fully realize the dynamic range

of the AD6650, it is recommended that the 24-bit mode be used.

Bit 3

By setting this bit high, the AD6650 becomes the serial bus

master. It is recommended that this bit be enabled (set high).

Bit 2 to Bit 0

This 3-bit register controls the divider on the serial clock

(SCLK) on the output of the AD6650. It is possible to divide the

SCLK by 8, allowing a flexible interface to a DSP or FPGA.

AD6650/PCB 数据表(PDF) 43 Page - Analog Devices

AD6650/PCB 数据表(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载