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AD6650

Rev. A | Page 29 of 44

CHIP SYNCHRONIZATION

The AD6650 is designed to allow synchronization of multiple

AD6650s within a system. The AD6650 is synchronized with

either a microprocessor write (Soft_SYNC) or a pulse on the

SYNC pin (Pin_SYNC). The first sync event starts the device,

and subsequent sync events resynchronize the filters of the

AD6650. By using a start holdoff counter, it is possible to align the

phase of the AD6650 to other devices. To synchronize the AD6650

with external hardware, see the Start with SYNC Pin section.

Start with Soft_SYNC

The AD6650 includes the ability to synchronize channels or

chips under microprocessor control. The start holdoff counter

(Address 0x14), in conjunction with the SYNC bit (External

Memory Address 5, Bit 0), allows this synchronization. The

start holdoff counter delays the start and synchronization of a

channel(s) by its value (number of AD6650 CLKs).

Use the following method to synchronize the start of a channel

via microprocessor control:

Set the appropriate channels to sleep mode. A hard reset to

the AD6650 (RESET taken low) puts both channels into

sleep mode.

Enable Channel A and/or Channel B (External Memory

Address 3, Bit 0).

Write the start holdoff counter(s) (Address 0x14) to the

appropriate value (greater than 1 but less than 65,535).

Program all other registers of the AD6650 that are not

already set.

Write the Soft_SYNC bit high (External Memory

Address 5, Bit 0).

When the Soft_SYNC bit goes high, the start holdoff

counter begins to count down using the AD6650 CLK

signal after the CLK divider. When the start holdoff

counter reaches a count of 1, the selected channel(s) are

activated.

Start with SYNC Pin

The AD6650 has a SYNC pin that can be used to provide

synchronization between AD6650 devices and external

hardware to a resolution of 1 ADC sample cycle. This can be

accomplished by providing a 1-CLK-cycle-wide pulse on the

SYNC pin when the edge-sensitive bit of the SF1 register is low

(External Memory Address 4, Bit 4), which is useful when an

FPGA or other external hardware is operating at the CLK rate of

the AD6650. Synchronization can also be accomplished by

setting the edge-sensitive bit high so that the SYNC input is

rising-edge sensitive, which is useful when the external

hardware is operating off a clock that is much slower than the

AD6650 or is asynchronous to it.

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