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AD6650/PCB 数据表(PDF) 7 Page - Analog Devices

部件名 AD6650/PCB
功能描述  GSM/EDGE Narrow-Band Receiver
PDF  45 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6650/PCB 数据表(HTML) 7 Page - Analog Devices

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AD6650
Rev. A | Page 6 of 44
MICROPROCESSOR PORT TIMING CHARACTERISTICS
All timing specifications valid over VDD range of 3.0 V to 3.45 V and VDDIO range of 3.0 V to 3.45 V.
Table 5. Microprocessor Port, Mode INM (MODE = 0); Asynchronous Operation
Parameter
Symbol
Temp
Test Level
Min
Typ
Max
Unit
WRITE TIMING
WR (R/W) to RDY (DTACK) Hold Time1
tHWR
Full
IV
0.0
ns
Address/Data to WR (R/W) Setup Time1
tSAM
Full
IV
0.0
ns
Address/Data to RDY (DTACK) Hold Time1
tHAM
Full
IV
0.0
ns
WR (R/W) to RDY (DTACK) Delay
tDRDY2
Full
IV
9.0
15.0
ns
WR (R/W) to RDY (DTACK) High Delay1
tACC
Full
IV
4 × tCLK
13 × tCLK
ns
READ TIMING
Address to RD (DS) Setup Time1
tSAM
Full
IV
0.0
ns
Address to Data Hold Time1
tHAM
Full
IV
0.0
ns
Data Three-state Delay1
tZD
Full
V
12
ns
RDY (DTACK) to Data Delay1
tDD
Full
IV
0.0
ns
RD (DS) to RDY (DTACK) Delay
tDRDY2
Full
IV
9.0
15.0
ns
RD (DS) to RDY (DTACK) High Delay1
tACC
Full
IV
4 × tCLK
13 × tCLK
ns
1 Timing is guaranteed by design.
2 Specification pertains to control signals R/W, WR, DS, RD, and CS such that the minimum specification is valid after the last control signal has reached a valid logic level.
Table 6. Microprocessor Port, Mode MNM (MODE = 1)
Parameter
Symbol
Temp
Test Level
Min
Typ
Max
Unit
WRITE TIMING
DS (RD) to DTACK (RDY) Hold Time
tHDS
Full
IV
15.0
ns
R/W (WR) to DTACK (RDY) Hold Time
tHRW
Full
IV
15.0
ns
Address/Data to R/W (WR) Setup Time1
tSAM
Full
IV
0.0
ns
Address/Data to R/W (WR) Hold Time1
tHAM
Full
IV
0.0
ns
DS (RD) to DTACK (RDY) Delay2
tDDTACK
Full
V
16
ns
R/W (WR) to DTACK (RDY) Low Delay1
tACC
Full
IV
4 × tCLK
13 × tCLK
ns
READ TIMING
DS (RD) to DTACK (RDY) Hold Time
tHDS
Full
IV
15.0
ns
Address to DS (RD) Setup Time1
tSAM
Full
IV
0.0
ns
Address to Data Hold Time1
tHAM
Full
IV
0.0
ns
Data Three-State Delay
tZD
Full
V
13
ns
DTACK (RDY) to Data Delay1
tDD
Full
IV
0.0
ns
DS (RD) to DTACK (RDY) Delay2
tDDTACK
Full
V
16
ns
DS (RD) to DTACK (RDY) Low Delay1
tACC
Full
IV
4 × tCLK
13 × tCLK
ns
1 Timing is guaranteed by design.
2
DTACK is an open-drain device and must be pulled up with a 1 kΩ resistor.



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