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AD6650

Rev. A | Page 22 of 44

LO SYNTHESIS

The AD6650 has a fully integrated quadrature LO synthesizer

consisting of a voltage-controlled oscillator (VCO) and a phase-

locked loop (PLL). Together these blocks generate quadrature

IF LO signals for the demodulators.

Figure 27 shows a block diagram of the LO synthesis block.

Besides the usual PLL and VCO, there is also a programmable

half-rate divider (Div-X and a fixed divide-by-4 quadrature

divider that produces the final I and Q LO signals).

VCO

The VCO generates an on-chip RF signal in the range of

2.2 GHz to 2.8 GHz. The only external component required is a

bypass capacitor for the low dropout (LDO) voltage regulator

used to power the VCO tank core. The VCO uses overlapping

bands to achieve the wide tuning range while maintaining

excellent phase noise and spurious performance. During band

selection, which takes 5 PFD cycles, the VCO VTUNE is disconnected

from the output of the loop filter and connected to an internal

reference voltage. After band select, normal PLL action

resumes. The nominal value of KV is 65 MHz/V, where KV is the

VCO sensitivity.

Immediately following the VCO is a programmable half-rate

divider that has settings of divide-by-2, -2.5, -3, -3.5, and so on,

up to divide-by-8. This function divides the VCO frequency

down to four times the LO frequency and effectively extends

the tuning range of the VCO. The VCO and the half-rate

divider can be thought of as a single lower frequency VCO with

a frequency range of 280 MHz to 1040 MHz.

Autocalibration selects both the VCO operating band and the

oscillator amplitude to ensure peak operating performance

across the entire frequency range. The half-rate divide setting is

also selected as part of the VCO calibration. Autocalibration is

performed whenever PLL Register 3 (the test mode latch) is

written; therefore, all other PLL registers should be set first, and

programming any portion of the LO synthesizer because the

VCO may need to recalibrate itself, depending on the changes

made to the registers.

PLL

The integer-N type PLL consists of a programmable reference

divider (R-divider), a prescaler and feedback divider (N-divider),

a phase-frequency detector (PFD), and a charge pump. The

output of the charge pump drives an external loop filter, which

in turn drives the input of the VCO.

R-Divider

The 14-bit R-divider divides down the input clock frequency to

produce the reference frequency for the phase-frequency

detector. Although division ratios from 1 to 16,383 are allowed,

the maximum update rate for the PFD is 1 MHz. The selected

update rate of the PFD and the subsequent charge pump

determines the spurious performance of the LO synthesizer;

therefore, the PFD reference frequency should be set for

optimal placement of spurs.

Prescaler and Feedback Dividers

The dual modulus prescaler, P/(P + 1), and the A and B

feedback dividers (5 bits and 13 bits, respectively) combine to

provide a wide ranging N-divider in the PLL feedback loop. The

feedback division is N = 8B + A. Including the final quadrature

divider (divide-by-4), the LO frequency is given by

(

)

CLK

8 +

(18)

where:

fLO

is the local oscillator frequency.

fCLK

is the external frequency oscillator.

is the 13-bit divider (3 to 8191).

is the 5-bit swallow divider (0 to 31).

is the input reference divider (1 to 16,384).

The fCLK/4R term combines the effects of the reference divider

and the final quadrature divider, and determines the frequency

spacing for the LO synthesizer. For a typical GSM application,

fCLK = 52 MHz and R = 65 result in a 200 kHz PFD update rate,

which sets the frequency spacing at a desired 200 kHz. However,

this also places LO spurs at offsets of 200 kHz multiples, which

might degrade the interferer/blocker performance.

R-DIV

14-BIT

B-DIV

13-BIT

A-DIV

5-BIT

PRESCALER

P/(P + 1)

PFD

CHARGE

PUMP

VCO

fCLK

IOUT

DIV-X

DIV-4

QOUT

CAL

fREF

EXTERNAL

LOOP FILTER

N-COUNTER

Figure 27. PLL Circuit

PFD and Charge Pump

The phase-frequency detector (PFD) takes inputs from the

R-divider and N-divider and produces an output proportional

to the phase and frequency difference between them. The PFD

includes a programmable delay element that controls the width

of the antibacklash pulse. This pulse ensures that there is no

dead zone in the PFD transfer function and minimizes

reference spurs.

Loop Filter

The final element in the LO synthesizer is the external loop

filter, which is generally a first-order or second-order RC low-

pass filter. A filter like the one shown in Figure 28 is recommended

to provide a good balance of stability, spurs, and phase noise.

This partiular filter is optimized for an update rate of 1 MHz.

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