AD6650SLASHPCB datasheet(38/45 Pages) AD

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AD6650

Rev. A | Page 37 of 44

Reg.

(Hex)

Mnemonic

Bit

Width

Description

Additional Information

Code

Count

65,534

Start Holdoff Counter

The power-up sequence is initiated with a

Soft_SYNC or Pin_SYNC and then the start

holdoff counter counts down to 1, and the

chip power-up sequence starts. 0 is an

invalid value.

65,535

Code

Decimation

CIC4 Decimation (MCIC4 − 1)

Should be ≥12 because CIC and IIR have

maximum rates of 26 MHz/12.

Code

Scale Factor

CIC4 Scale (Scale − 12)

Controls the attenuation of the data into the

CIC4 stage in 6 dB increments. This register

has a range of 12 to 20, which supports

decimations from 8 to 32 according to

Equation 4.

Code

Results

IIR Control

Sync mask.

Disabled

Enabled

Code

Decimation

Decimation of 1 to 8.

RCF Decimation Register

(MRCF − 1)

Code

Phase

Phase from 0 to MRCF − 1.

RCF Decimation Phase

(PRCF)

Code

Offset

Range is 0 to 48 taps.

RCF Coefficient Offset

(CORCF)

AD6650/PCB 数据表(PDF) 38 Page - Analog Devices

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AD6650/PCB 数据表(PDF) 38 Page - Analog Devices

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