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STV3550 数据表(PDF) 103 Page - STMicroelectronics |
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STV3550 数据表(HTML) 103 Page - STMicroelectronics |
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103 / 144 page  STV3550 103/144 the value has changed between the previous and current values, then an edge is detected. This is illustrated in Figure 66. 7.7.8 Receive Data Sampling The data received by the SSC2 is sampled after the latching edge of the input clock. The latching edge being determined by the programming of the polarity and phase bits. The data value which is finally latched is determined by taking 3 data samples at the 3rd, 4th and 5th system clock periods after the latching data edge. The data value is determined from the predominant data value in the 3 samples. This therefore gives an element of spike suppression. The sampling process is shown in Figure 67. Figure 66: Clock Edge Detection (Rising Edge) Figure 67: Receive Data Sampling System Clock Serial_Clock_In Sampling Points 12 3 4 First 3 samples Majority 0 Last 3 samples Majority 1 System Clock Serial_Clock_In Sampling Points Latched Data Value 12 3 |
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