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EDBA164B4PR-1DATF-R 数据表(PDF) 41 Page - Micron Technology |
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EDBA164B4PR-1DATF-R 数据表(HTML) 41 Page - Micron Technology |
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41 / 152 page ![]() Table 40: MR17 PASR Segment Mask (MA[7:0] = 011h) OP7 OP6 OP5 OP4 OP3 OP2 OP1 OP0 Segment mask Note: 1. This table applies for 1Gb to 8Gb devices only. Table 41: MR17 PASR Segment Mask Definitions (1Gb - 8Gb only) Feature Type OP Definition Segment[7:0] mask Write-only OP[7:0] 0b: refresh enable to the segment: = unmasked (default) 1b: refresh blocked: = masked Table 42: MR17 PASR Row Address Ranges in Masked Segments Segment OP Segment Mask 1Gb 2Gb, 4Gb 8Gb R[12:10] R[13:11] R[14:12] 0 0 XXXXXXX1 000b 1 1 XXXXXX1X 001b 2 2 XXXXX1XX 010b 3 3 XXXX1XXX 011b 4 4 XXX1XXXX 100b 5 5 XX1XXXXX 101b 6 6 X1XXXXXX 110b 7 7 1XXXXXXX 111b Note: 1. X is “Don’t Care” for the designated segment. 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Mode Register Definition 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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