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EDBA164B4PR-1DATF-R 数据表(PDF) 96 Page - Micron Technology |
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EDBA164B4PR-1DATF-R 数据表(HTML) 96 Page - Micron Technology |
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96 / 152 page  Table 54: Command Truth Table (Continued) Notes 1–13 apply to all parameters conditions Command Command Pins CA Pins CK Edge CKE CS_n CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 CK(n-1) CK(n) Exit PD, SREF, DPD LH H X XH X X Notes: 1. All commands are defined by the current state of CS_n, CA0, CA1, CA2, CA3, and CKE at the rising edge of the clock. 2. Bank addresses (BA) determine which bank will be operated upon. 3. AP HIGH during a READ or WRITE command indicates that an auto precharge will occur to the bank associated with the READ or WRITE command. 4. X indicates a “Don’t Care” state, with a defined logic level, either HIGH (H) or LOW (L). 5. Self refresh exit and DPD exit are asynchronous. 6. VREF must be between 0 and VDDQ during self refresh and DPD operation. 7. CAxr refers to command/address bit “x” on the rising edge of clock. 8. CAxf refers to command/address bit “x” on the falling edge of clock. 9. CS_n and CKE are sampled on the rising edge of the clock. 10. Per-bank refresh is supported only in devices with eight banks. 11. The least-significant column address C0 is not transmitted on the CA bus, and is inferred to be zero. 12. RFU needs to input “H” or “L“ (but a defined logic level). 13. AB “high”during Precharge command indicates that all bank Precharge will occur. In this case, Bank Address is don’t care. Table 55: CKE Truth Table Notes 1–5 apply to all parameters and conditions; L = LOW, H = HIGH, X = “Don’t Care” Current State CKEn-1 CKEn CS_n Command n Operation n Next State Notes Active power-down L L X X Maintain active power-down Active power-down L H H NOP Exit active power-down Active 6, 7 Idle power- down L L X X Maintain idle power-down Idle power-down L H H NOP Exit idle power-down Idle 6, 7 Resetting idle power-down L L X X Maintain resetting power-down Resetting power-down L H H NOP Exit resetting power-down Idle or resetting 6, 7, 8 Deep power- down L L X X Maintain deep power-down Deep power-down L H H NOP Exit deep power-down Power-on 9 Self refresh L L X X Maintain self refresh Self refresh L H H NOP Exit self refresh Idle 10, 11 Bank(s) active H L H NOP Enter active power-down Active power-down 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Truth Tables 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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