EDBA164B4PR-1DATF-R datasheet(86/152 Pages) MICRON

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Figure 56: Power-Down Entry and Exit Timing

Exit

Valid

NOP

Enter

NOP

Enter power-down mode

Input clock frequency can be changed

or the input clock can be stopped during power-down.

Valid

CK_t

CKE

CS_n

CMD

tCKE(MIN)

tXP(MIN)

tCKE(MIN)

2 tCK(MIN)

tIHCKE

Exit power-down mode

Don’t Care

tISCKE

CK_c

Note:

1. Input clock frequency can be changed or the input clock stopped during power-down,

provided that the clock frequency is between the minimum and maximum specified fre-

quencies for the speed grade in use, and that prior to power-down exit, a minimum of

two stable clocks complete.

Figure 57: CKE Intensive Environment

CK_c

CKE

tCKE

CK_t

Figure 58: REFRESH-to-REFRESH Timing in CKE Intensive Environments

CK_c

CKE

CMD

tCKE

REFRESH

tXP

tREFI

tXP

CK_t

Note:

1. The pattern shown can repeat over an extended period of time. With this pattern, all

AC and DC timing and voltage specifications with temperature and voltage drift are en-

sured.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Power-Down

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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