EDBA164B4PR-1DATF-R datasheet(60/152 Pages) MICRON

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Figure 37: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(tRTP(MIN)/tCK) = 3

Bank m

col addr a Col addr a

READ

NOP

CK_c

CK_t

CA[9:0]

CMD

DQS_c

DQS_t

RL = 3

tRP

Transitioning data

NOP

PRECHARGE

NOP

tRTP = 3

BL/2

ACTIVATE

OUT A0

OUT A1

OUT A2

OUT A3

NOP

Bank m

row addr

Row addr

WRITE Burst Followed by PRECHARGE

For WRITE cycles, a WRITE recovery time ( tWR) must be provided before a PRECHARGE

command can be issued. tWR delay is referenced from the completion of the burst

WRITE. The PRECHARGE command must not be issued prior to the tWR delay. For

WRITE-to-PRECHARGE timings, see the PRECHARGE and Auto Precharge Clarification

table.

These devices write data to the array in prefetch quadruples (prefetch = 4). An internal

WRITE operation can only begin after a prefetch group has been completely latched.

The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL +

BL/2 + 1 + RU(tWR/tCK) clock cycles. For untruncated bursts, BL is the value set in the

mode register. For truncated bursts, BL is the effective burst length.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

PRECHARGE Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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