EDBA164B4PR-1DATF-R datasheet(14/152 Pages) MICRON

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Table 7: IDD Specifications – Dual Die, Dual Channel (Continued)

VDD2, VDDQ = 1.14–1.30V; VDD1 = 1.70–1.95V; TC = –40°C to +105°C

Symbol

Supply

Speed

Unit

Parameter/Condition

1066

IDD3NS1

VDD1

2.8

All devices in active non power-down standby current

with clock stop

CK_t = LOW, CK_c = HIGH; CKE is HIGH;

CS_n is HIGH; One bank is active;

CA bus inputs are STABLE;

Data bus inputs are STABLE

IDD3NS2

VDD2, VDDQ

IDD4R1

VDD1

All devices in operating burst read

tCK = tCK(avg) MIN;

CS_n is HIGH between valid commands;

One bank is active; BL = 4; RL = RL (MIN);

CA bus inputs are SWITCHING;

50% data change occurs at each burst transfer

IDD4R2

VDD2, VDDQ

840

IDD4W1

VDD1

All devices in operating burst write

tCK = tCK(avg) MIN;

CS_n is HIGH between valid commands;

One bank is active; BL = 4; WL = WL (MIN);

CA bus inputs are SWITCHING;

50% data change occurs at each burst transfer

IDD4W2

VDD2, VDDQ

300

IDD51

VDD1

All devices in all bank auto-refresh

tCK = tCK(avg) MIN;

CKE is HIGH between valid commands;

tRC = tRFCab (MIN); Burst refresh;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD52

VDD2, VDDQ

240

IDD5AB1

VDD1

All devices in all bank auto-refresh

tCK = tCK(avg) MIN;

CKE is HIGH between valid commands;

tRC = tREFI;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD5AB2

VDD2, VDDQ

IDD5PB1

VDD1

All devices in per bank auto-refresh

tCK = tCK(avg) MIN;

CKE is HIGH between valid commands;

tRC = tREFIpb;

CA bus inputs are SWITCHING;

Data bus inputs are STABLE

IDD5PB2

VDD2, VDDQ

Notes:

1. Published IDD values are the maximum of the distribution of the arithmetic mean.

2. IDD current specifications are tested after the device is properly initialized.

3. VDD2 and VDDQ are connected internally in the package.

4. The Quad die product IDD for each channel will be the sum of the IDD's for the state of

operation for each rank (CS) in the channel.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

IDD Specifications

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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