EDBA164B4PR-1DATF-R datasheet(94/152 Pages) MICRON

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Input Clock Frequency Changes and Clock Stop with CKE HIGH

During CKE HIGH, the LPDDR2 device supports input clock frequency changes and

clock stop under the following conditions:

• REFRESH requirements are met

• Any ACTIVATE, READ, WRITE, PRECHARGE, MRW, or MRR commands must have

completed, including any associated data bursts, prior to changing the frequency

• Related timing conditions, tRCD, tWR, tRP, tMRW, and tMRR, etc., are met

• CS_n must be held HIGH

• Only REFab or REFpb commands can be in process

The device is ready for normal operation after the clock satisfies tCH(abs) and tCL(abs)

for a minimum of 2 × tCK + tXP.

For input clock frequency changes, tCK(MIN) and tCK(MAX) must be met for each clock

cycle.

After the input clock frequency is changed, additional MRW commands may be re-

quired to set the WR, RL, etc. These settings may require adjustment to meet minimum

timing requirements at the target clock frequency.

For clock stop, CK_t is held LOW and CK_c is held HIGH.

NO OPERATION Command

The NO OPERATION (NOP) command prevents the device from registering any unwan-

ted commands issued between operations. A NOP command can be issued only at

clock cycle N when the CKE level is constant for clock cycle N-1 and clock cycle N. The

NOP command has two possible encodings: CS_n HIGH at the clock rising edge N; and

CS_n LOW with CA0, CA1, CA2 HIGH at the clock rising edge N.

The NOP command will not terminate a previous operation that is still in process, such

as a READ burst or WRITE burst cycle.

Truth Tables

Truth tables provide complementary information to the state diagram. They also clarify

device behavior and applicable restrictions when considering the actual state of the

banks.

Unspecified operations and timings are illegal. To ensure proper operation after an ille-

gal event, the device must be powered down and then restarted using the specified initi-

alization sequence before normal operation can continue.

Table 54: Command Truth Table

Notes 1–13 apply to all parameters conditions

Command

Command Pins

CA Pins

Edge

CKE

CS_n

CA0

CA1

CA2

CA3

CA4

CA5

CA6

CA7

CA8

CA9

CK(n-1) CK(n)

MRW

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

OP0

OP1

OP2

OP3

OP4

OP5

OP6

OP7

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

NO OPERATION Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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