SPC58ECX datasheet(52/153 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC584Cx, SPC58ECx

52/153

DS11620 Rev 8

ΔTUE12

TUE degradation due

to VDD_HV_ADR offset

with respect to

VDD_HV_ADV

VIN < VDD_HV_ADV

VDD_HV_ADR − VDD_HV_ADV

∈ [0:25 mV]

–1

LSB

(12b)

VIN < VDD_HV_ADV

VDD_HV_ADR − VDD_HV_ADV

∈ [25:50 mV]

–2

VIN < VDD_HV_ADV

VDD_HV_ADR − VDD_HV_ADV

∈ [50:75 mV]

–4

VIN < VDD_HV_ADV

VDD_HV_ADR − VDD_HV_ADV

∈ [75:100 mV]

–6

VDD_HV_ADV < VIN <

VDD_HV_ADR

VDD_HV_ADR − VDD_HV_ADV

∈ [0:25 mV]

–2.5

2.5

VDD_HV_ADV < VIN <

VDD_HV_ADR

VDD_HV_ADR − VDD_HV_ADV

∈ [25:50 mV]

–4

VDD_HV_ADV < VIN <

VDD_HV_ADR

VDD_HV_ADR − VDD_HV_ADV

∈ [50:75 mV]

–7

VDD_HV_ADV < VIN <

VDD_HV_ADR

VDD_HV_ADR − VDD_HV_ADV

∈ [75:100 mV]

–12

DNL(8)

Differential non-

linearity

Standard frequency mode,

VDD_HV_ADV > 4 V

VDD_HV_ADR_S > 4 V

–1

LSB

(12b)

High frequency mode,

VDD_HV_ADV > 4 V

VDD_HV_ADR_S > 4 V

–1

1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal

sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within

the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing

and calculating the sampling window duration.

2. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz.

3. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz.

4. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz.

5. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven

by the transfer of charge between internal capacitances during the conversion.

6. Current parameter values are for a single ADC.

Table 27. SARn ADC electrical specification (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

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