SPC58ECX datasheet(94/153 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC584Cx, SPC58ECx

94/153

DS11620 Rev 8

4.17.3.1

MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at least

equal to or greater than the RX_CLK frequency.

Note:

In the following table, all timing specifications are referenced from RX_CLK = 1.4 V to the

valid input levels, 0.8 V and 2.0 V.

Figure 35. MII receive signal timing diagram

4.17.3.2

MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at least

equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from

either the rising or falling edge of TX_CLK, and the timing is the same in either case. This

option allows the use of non-compliant MII PHYs.

Refer to the SPC584Cx and SPC58ECx 32-bit Power Architecture microcontroller reference

manual’s

Ethernet chapter for details of this option and how to enable it.

Note:

In the following table, all timing specifications are referenced from TX_CLK = 1.4 V to the

valid output levels, 0.8 V and 2.0 V.

Table 50. MII receive signal timing

Symbol

Characteristic

Value

Unit

Min

Max

CC D RXD[3:0], RX_DV, RX_ER to RX_CLK setup

—

CC D RX_CLK to RXD[3:0], RX_DV, RX_ER hold

—

CC D RX_CLK pulse width high

35%

65%

RX_CLK period

CC D RX_CLK pulse width low

35%

65%

RX_CLK period

RX_CLK (input)

RXD[3:0] (inputs)

RX_DV

RX_ER

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