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SPC58ECX 数据表(PDF) 91 Page - STMicroelectronics |
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SPC58ECX 数据表(HTML) 91 Page - STMicroelectronics |
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91 / 153 page  DS11620 Rev 8 91/153 SPC584Cx, SPC58ECx Electrical characteristics 105 Figure 30. DSPI CMOS master mode — modified timing, CPHA = 0 Figure 31. DSPI CMOS master mode — modified timing, CPHA = 1 10. Due to timing delay, a slave could not have enough margin while sampling and only for the following DSPI4 PAD combinations: (SOUT: PAD[63] and SCK: PAD[57] or PAD[137] or PAD[161] or PAD[208]) the Tsuo values have to be increased by 2.5ns. For all the other DSPI pads combinations the Tsuo has to be increased by 1.5ns. 11. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. Data Last Data First Data First Data Data Last Data SIN SOUT PCSx SCK Output SCK Output (CPOL = 0) (CPOL = 1) tSCK tSDC tSDC tCSC tASC tSUI tHI tSUO tHO Data Last Data First Data SIN SOUT Last Data Data First Data SCK Output SCK Output PCSx (CPOL = 0) (CPOL = 1) tSUI tHI tSUO tHO tHI |
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