SPC58ECX datasheet(77/153 Pages) STMICROELECTRONICS

77 / 153 page

DS11620 Rev 8

77/153

SPC584Cx, SPC58ECx

Electrical characteristics

105

4.17

AC Specifications

All AC timing specifications are valid up to 150 °C, except where explicitly noted.

4.17.1

Debug and calibration interface timing

4.17.1.1

JTAG interface timing

Table 43. JTAG pin AC electrical characteristics

Symbol

Characteristic

Value(1),(2)

Unit

Min

Max

1tJCYC

CC D TCK cycle time

100

—

2tJDC

CC T TCK clock pulse width

3tTCKRISE

CC D TCK rise and fall times (40%–70%)

—

4tTMSS, tTDIS CC D TMS, TDI data setup time

—

5tTMSH, tTDIH CC D TMS, TDI data hold time

—

6tTDOV

CC D TCK low to TDO data valid

—

15(3)

7tTDOI

CC D TCK low to TDO data invalid

—

8tTDOHZ

CC D TCK low to TDO high impedance

—

9tJCMPPW

CC D JCOMP assertion time

100

—

tJCMPS

CC D JCOMP setup time to TCK low

—

tBSDV

CC D TCK falling edge to output valid

—

600(4)

tBSDVZ

CC D TCK falling edge to output valid out of high impedance

—

600

tBSDHZ

CC D TCK falling edge to output high impedance

—

600

tBSDST

CC D Boundary scan input valid to TCK rising edge

—

tBSDHT

CC D TCK rising edge to boundary scan input invalid

—

1. These specifications apply to JTAG boundary scan only. See Table 44 for functional specifications.

2. JTAG timing specified at VDD_HV_IO_JTAG = 4.0 to 5.5 V and max. loading per pad type as specified in the I/O section of the

datasheet.

3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

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