SPC58ECX datasheet(62/153 Pages) STMICROELECTRONICS

部件名	SPC58ECX

功能描述	SPC58 C Line - 32 bit Power Architecture automotive MCU Dual z4 cores 180 MHz, 4 MBytes Flash, HSM, ASIL-B

PDF	153 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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62 / 153 page

Electrical characteristics

SPC584Cx, SPC58ECx

62/153

DS11620 Rev 8

ΔPERREF SR

Input reference clock jitter (peak to peak)

Single period,

fRF_REF =20MHz

——

350

Long term,

fRF_REF =20MHz

-500

—

500

ΔPEREYE CC T

Output Eye Jitter (peak to peak)(5)

——

—

400

1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.

2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1.

3. The 320 MHz frequency is achieved with a 20 MHz reference clock.

4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral

bridge clock that is connected to the PLL on the device (to set the PLL enable bit).

5. Measured at the transmitter output across a 100

Ω termination resistor on a device evaluation board. See Figure 12.

Table 32. LFAST PLL electrical characteristics (continued)

Symbol(1)

Parameter

Conditions

Value

Unit

Min

Typ

Max

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