SPC58ECX datasheet(84/153 Pages) STMICROELECTRONICS

84 / 153 page

Electrical characteristics

SPC584Cx, SPC58ECx

84/153

DS11620 Rev 8

4.17.2.1

DSPI master mode full duplex timing with CMOS pads

4.17.2.1.1 DSPI CMOS master mode – classic timing

Note:

In the following table, all output timing is worst case and includes the mismatching of rise

and fall times of the output pads.

Table 46. DSPI channel frequency support

DSPI use mode(1)

Max usable

frequency

(MHz)(2),(3)

CMOS (Master

mode)

Full duplex – Classic timing (Table 47)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

DSPI_5, DSPI_6,

DSPI_7

DSPI_4

Full duplex – Modified timing (Table 48)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

DSPI_5, DSPI_6,

DSPI_7

DSPI_4

Output only mode (SCK/SOUT/PCS) (Table 47 and

Table 48

)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

DSPI_5, DSPI_6,

DSPI_7

DSPI_4

Output only mode TSB mode (SCK/SOUT/PCS)

DSPI_0, DSPI_1,

DSPI_2, DSPI_3,

DSPI_5, DSPI_6,

DSPI_7

DSPI_4

CMOS (Slave mode Full duplex) (Table 49)—

1. Each DSPI module can be configured to use different pins for the interface. Refer to the device pinout Microsoft Excel file

attached to the IO_Definition document for the available combinations. It is not possible to reach the maximum

performance with every possible combination of pins.

2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

3. Maximum usable frequency does not take into account external device propagation delay.

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