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SPC58ECX 数据表(PDF) 40 Page - STMicroelectronics |
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SPC58ECX 数据表(HTML) 40 Page - STMicroelectronics |
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40 / 153 page  Electrical characteristics SPC584Cx, SPC58ECx 40/153 DS11620 Rev 8 4.10 PLLs Two phase-locked loop (PLL) modules are implemented to generate system and auxiliary clocks on the device. Figure 7 depicts the integration of the two PLLs. Refer to device Reference Manual for more detailed schematic. Figure 7. PLLs integration 4.10.1 PLL0 PLL0 PLL1 IRCOSC XOSC PLL1_PHI PLL0_PHI1 PLL0_PHI Table 20. PLL0 electrical characteristics Symbol C Parameter Conditions Value Unit Min Typ Max fPLL0IN SR — PLL0 input clock(1) —8 — 44 MHz ΔPLL0IN SR — PLL0 input clock duty cycle(1) —40 — 60 % fINFIN SR — PLL0 PFD (Phase Frequency Detector) input clock frequency —8 — 20 MHz fPLL0VCO CC P PLL0 VCO frequency — 600 — 1400 MHz fPLL0PHI0 CC D PLL0 output frequency — 4.762 — 400 MHz fPLL0PHI1 CC D PLL0 output clock PHI1 — 20 — 175(2) MHz tPLL0LOCK CC P PLL0 lock time — — — 100 µs |ΔPLL0PHI0SPJ|(3) CC T PLL0_PHI0 single period jitter fPLL0IN = 20 MHz (resonator) fPLL0PHI0 = 400 MHz, 6-sigma pk-pk — — 200 ps |
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