SPC58ECX datasheet(11/153 Pages) STMICROELECTRONICS

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DS11620 Rev 8

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SPC584Cx, SPC58ECx

Description

2.3

Features overview

On-chip modules within SPC584Cx and SPC58ECx include the following features:

•

Two main CPUs, dual issue, 32-bit CPU core complexes (e200z4).

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Power Architecture embedded specification compliance

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Instruction set enhancement allowing variable length encoding (VLE), encoding a

mix of 16-bit and 32-bit instructions, for code size footprint reduction

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Single-precision floating point operations

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64 KB local data RAM for Core_0 and Core_2

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8 KB I-Cache and 4 KB D-Cache for Core_0 and Core_2

•

4224 KB (4096 KB code flash + 128 KB data flash) on-chip flash memory

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Supports read during program and erase operations, and multiple blocks allowing

EEPROM emulation

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176 KB HSM dedicated flash memory (144 KB code + 32 KB data)

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384 KB on-chip general-purpose SRAM (+ 128 KB local data RAM: 64 KB included in

each CPU)

•

Multi channel direct memory access controllers

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64 eDMA channels

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One interrupt controller (INTC)

•

Dual phase-locked loops with stable clock domain for peripherals and FM modulation

domain for computational shell

•

Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from

multiple bus masters with end-to-end ECC

•

Hardware security module (HSM) with HW cryptographic co-processor

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System integration unit lite (SIUL)

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Boot assist Flash (BAF) supports factory programming using a serial bootload through

the asynchronous CAN or LIN/UART.

•

Hardware support for safety ASIL-B level related applications

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Enhanced modular IO subsystem (eMIOS): up to 64 (2 x 32) timed I/O channels with

16-bit counter resolution

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Buffered updates

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Support for shifted PWM outputs to minimize occurrence of concurrent edges

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Supports configurable trigger outputs for ADC conversion for synchronization to

channel output waveforms

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Shared or independent time bases

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DMA transfer support available

•

Body cross triggering unit (BCTU)

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Triggers ADC conversions from any eMIOS channel

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Triggers ADC conversions from up to 2 dedicated PIT_RTIs

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One event configuration register dedicated to each timer event allows to define the

corresponding ADC channel

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Synchronization with ADC to avoid collision

•

Enhanced analog-to-digital converter system with:

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Three independent fast 12-bit SAR analog converters

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