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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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SPC58ECX 数据表(PDF) 95 Page - STMicroelectronics |
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SPC58ECX 数据表(HTML) 95 Page - STMicroelectronics |
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95 / 153 page  DS11620 Rev 8 95/153 SPC584Cx, SPC58ECx Electrical characteristics 105 Figure 36. MII transmit signal timing diagram 4.17.3.3 MII async inputs signal timing (CRS and COL) Figure 37. MII async inputs timing diagram Table 51. MII transmit signal timing Symbol C Characteristic Value(1) Unit Min Max M5 CC D TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 — ns M6 CC D TX_CLK to TXD[3:0], TX_EN, TX_ER valid — 25 ns M7 CC D TX_CLK pulse width high 35% 65% TX_CLK period M8 CC D TX_CLK pulse width low 35% 65% TX_CLK period 1. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25pF value M6 TX_CLK (input) TXD[3:0] (outputs) TX_EN TX_ER M5 M7 M8 Table 52. MII async inputs signal timing Symbol C Characteristic Value Unit Min Max M9 CC D CRS, COL minimum pulse width 1.5 — TX_CLK period CRS, COL M9 |
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