ST25R3916 datasheet(47/157 Pages) STMICROELECTRONICS

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DS12484 Rev 4

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ST25R3916/7

Application information

156

4.3

Communication with an external microcontroller

The ST25R3916/7 communicate with a microcontroller either via an SPI interface or via an

I2C interface. On both interfaces the ST25R3916/7 act as slave devices, relying on the

microcontroller to initiate all communication. To notify the microcontroller of completed

commands or external events (e.g. peer device field on) the ST25R3916/7 signal an

interrupt on the IRQ pin. The ST25R3916/7 can also provide a configurable clock signal to

the microcontroller on the MCU_CLK pin.

4.3.1

Interrupt interface

There are four interrupt registers implemented in the ST25R3916/7:



Main interrupt register



Timer and NFC interrupt register



Error and wake-up interrupt register



Passive target interrupt register

When an interrupt condition is met the source of interrupt bit is set and the IRQ pin

transitions to high. The microcontroller then reads the Main interrupt register to distinguish

between different interrupt sources. After a particular interrupt register is read, its content is

reset to 0.

The IRQ pin transitions to low after the interrupt bit(s) that caused its transition to high has

(have) been read.

Note:

There may be more than one interrupt bit set if the microcontroller does not immediately

read the interrupt registers after the IRQ signal is set and another event causing an interrupt

occurs. In this case the IRQ pin transitions to low after the last bit causing interrupt is read.

If an interrupt from a certain source is not required it can be disabled by setting the

corresponding bit in the Mask interrupt registers. In case of masking a certain interrupt

source the IRQ line is not set high, but the interrupt status bit is still set in IRQ status

registers.

Reading the IRQ status registers presents and clears also the masked interrupt bits.

If some interrupts are masked, and set to 1 because of an IRQ event, and later on one of

them unmasks the IRQ status bit that is already set, the IRQ line is immediately set to high.

This notifies the host system that there are some interrupt events not yet read out.

IRQ line and IRQ status bits are cleared at:



Set default



Reading the IRQ status



Stop all activities



Clear FIFO.

Table 9. IRQ output

Name

Signal

Level

Description

IRQ

Digital output

CMOS

Interrupt output pin

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