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ST25R3916 数据表(PDF) 55 Page - STMicroelectronics

部件名 ST25R3916
功能描述  High performance NFC universal device and EMVCo™ reader
PDF  157 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST25R3916 数据表(HTML) 55 Page - STMicroelectronics

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DS12484 Rev 4
55/157
ST25R3916/7
Application information
156
Writing data to addressable registers (Register Write mode)
After the I2C slave address the address of the register to be written is sent using the same
Register Write mode byte as for SPI register write access. The Register Write mode byte is
then followed by one or more data bytes. If more than one data byte is sent, the data is
stored in subsequent registers starting form the initial register address by incrementing the
target address by one for each new data byte.
Figure 20 and Figure 21 show, respectively, how to write a single byte into a register and
how to write multiple bytes into subsequent registers using address auto-incrementing.
Figure 20. Writing a single register
Figure 21. Writing register data with auto-incrementing address
Reading data from addressable registers (Register Read mode)
After the I2C slave address the address of the register to be read is sent using the same
Register Read mode byte of the SPI register read access. After the Register Read mode
byte the ST25R3916/7 sends data bytes to the SDA output as long as the MCU keeps SCL.
The Register Read mode also supports address auto-incrementing. If the addressed
register does not exist, all 0 data is sent to SDA.
Table 12. I2C interface and interrupt signal lines
Name
Signal
Signal level
Description
I2C_EN
Digital input
CMOS
Pull to VDD_D for I2C operation
MISO (SDA)
Digital output
I2C data line
SCLK (SCL)
Digital input
I2C clock
IRQ
Digital output
Active high - Interrupt output pin
MS51653V2
SCL
SDA
0
0
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
R
4
R
3
R
2
R
1
A
C
K
P
S
Slave address
D
7
D
6
D
5
D
4
D
3
D
2
R
0
A
C
K
D
1
D
0
Data
Register address
A
C
K
R
5
MS51654V3
SCL
SDA
0 0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
R
4
R
3
R
2
R
1
A
C
K
P
S
Data moved to address
<R5-R0> + n
Slave address
D
7
D
6
D
5
D
4
D
3
D
2
R
0
A
C
K
D
1
D
0
D
3
D
2
D
1
D
0
A
C
K
D
5
D
4
D
7
D
6
Data moved to address
<R5-R0> + 0
Register address
R
5
A
C
K



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