ST25R3916 datasheet(77/157 Pages) STMICROELECTRONICS

77 / 157 page

DS12484 Rev 4

77/157

ST25R3916/7

Application information

156

4.5.7

ISO14443B settings register 1

Address: 06h

Type: RW

001

000

Table 28. ISO14443A modulation pulse width (continued)

p_len3

p_len2

p_len1

p_len0

Pulse width in number of 1 / fc for different bit rates

fc / 128

fc / 64

fc / 32

fc / 16

Table 29. ISO14443B settings register 1

Bit

Name

Default

Function

Comments

egt2

egt1

egt0

Number of etu

EGT defined in number of etu

egt1

egt0

sof_0

0: 10 etu

1: 11 etu

SOF, number of etu with logic 0

sof_1

0: 2 etu

1: 3 etu

SOF, number of etu with logic 1

2eof

0: 10 etu

1: 11 etu

EOF, number of etu with logic 0

half

0: SOF and EOF defined by sof_0, sof_1,

and eof bit

1: SOF 10.5 etu logic 0, 2.5 etu logic 1,

EOF: 10.5 etu logic 0

Sets SOF and EOF settings in middle of

specification.

0rx_st_om

0: Start/stop bit must be present for Rx

1: Start/stop bit omission for Rx

SOF fixed to 10 low and 2 etu high, EOF

not defined, put in FIFO last full byte

CRC is not checked in this mode.

Supported only in a coherent reception

mode.

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