ST25R3916 datasheet(102/157 Pages) STMICROELECTRONICS

102 / 157 page

Application information

ST25R3916/7

102/157

DS12484 Rev 4

4.5.38

FIFO status register 1

Address: 1Eh

Type: R

4.5.39

FIFO status register 2

Address: 1Fh

Type: R

Table 66. FIFO status register 1

Bit

Name

Default

Function

Comments

fifo_b7

Number of bytes in the FIFO

(LSB)

Valid range is from 0 to 512.

fifo_b6

fifo_b5

fifo_b4

fifo_b3

fifo_b2

fifo_b1

fifo_b0

Table 67. FIFO status register 2

Bit

Name

Default

Function

Comments

fifo_b9

Number of bytes in the FIFO

(MSB)

fifo_b8

fifo_unf

1: FIFO underflow

fifo_ovr

1: FIFO overflow

3fifo_lb2

Number of bits in the last FIFO

byte if it was not complete

The received bits are stored in the LSB part of

the last byte in the FIFO.

If I_err1 is set then fifo_lb<2:0> dos not contain

valid data.

2fifo_lb1

1fifo_lb0

0np_lb

1: Parity bit is missing in the last

byte

The bit is set if the last received byte is complete

with 8 data bits but he parity bit is missing.

If I_err1 is set then np_lb does not contain valid

data.

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