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ST25R3916 数据表(PDF) 146 Page - STMicroelectronics |
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ST25R3916 数据表(HTML) 146 Page - STMicroelectronics |
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146 / 157 page  Electrical characteristics ST25R3916/7 146/157 DS12484 Rev 4 Table 130. 100 kHz AC characteristics(1) Symbol Alt. Parameter Min Max Unit fC fSCL Clock frequency - 100 kHz tCHCL tHIGH Clock pulse width high 4000 - ns tCLCH tLOW Clock pulse width low 4700 - tQL1QL2 tF SDA (out) fall time - 300 tDXCH tSU:DAT Data in set up time 250 - tCLDXXtHD:DAT Data in hold time 5000 - tCLQX tDH Data out hold time 50 - tCLQV tAA Clock low to next data valid (access time) - 3450 tCHDL tSU:STA Start condition setup time 4700 - tDLCL tHD:STA Start condition hold time 4000 - tCHDH tSU:STO Stop condition set up time 4000 - tDHDL tBUF Time between Stop condition and next Start condition 4700 - tNS(2) - Pulse width ignored (input filter on SCL and SDA), single glitch -40 1. Conditions in addition to those specified in Table 126 and Table 127. 2. Evaluated by characterization, not tested in production. Table 131. 400 kHz AC characteristics(1) (2) Symbol Alt. Parameter Min Max Unit fC fSCL Clock frequency - 400 kHz tCHCL tHIGH Clock pulse width high 600 - ns tCLCH tLOW Clock pulse width low 1300 - tQL1QL2 tF SDA (out) fall time - 300 tDXCH tSU:DAT Data in set up time 100 - tCLDXXtHD:DAT Data in hold time 0 - tCLQX tDH Data out hold time 50 - tCLQV tAA Clock low to next data valid (access time) - 900 tCHDL tSU:STA Start condition setup time 600 - tDLCL tHD:STA Start condition hold time 600 - tCHDH tSU:STO Stop condition set up time 600 - tDHDL tBUF Time between Stop condition and next Start condition 1300 - tNS - Pulse width ignored (input filter on SCL and SDA), single glitch -40 1. Conditions in addition to those specified in Table 126 and Table 127. 2. Evaluated by characterization, not tested in production. |
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