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ST7LUS5 数据表(PDF) 46 Page - STMicroelectronics |
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ST7LUS5 数据表(HTML) 46 Page - STMicroelectronics |
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46 / 124 page  Power saving modes ST7LUS5, ST7LU05, ST7LU09 46/124 Figure 18. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 8.4 Active Halt and Halt modes Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active Halt or Halt mode is given by the LTCSR/ATCSR register status as shown in the following table: WFI INSTRUCTION RESET INTERRUPT Y N N Y CPU OSCILLATOR PERIPHERALS IBIT ON ON 0 OFF FETCH RESET VECTOR OR SERVICE INTERRUPT CPU OSCILLATOR PERIPHERALS IBIT ON OFF 0 ON CPU OSCILLATOR PERIPHERALS IBIT ON ON X (1) ON 64 CPU CLOCK CYCLE DELAY Table 21. LTC/ATC low power mode selection LTCSR TBIE bit ATCSR OVFIE bit ATCSRCK1 bit ATCSRCK0 bit Meaning 0x x0 Active Halt mode disabled 00 x x 01 11 1x x x Active Halt mode enabled x1 0 1 |
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