ST7LUS5 datasheet(36/124 Pages) STMICROELECTRONICS

36 / 124 page

Supply, reset and clock management

ST7LUS5, ST7LU05, ST7LU09

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6.4

6.4.1

Multiplexed I/O reset control register 1 (MUXCR1)

6.4.2

Multiplexed I/O reset control register 0 (MUXCR0)

MUXCR1

Reset value: 0000 0000 (00h)

765432

MIR[15:8]

Read / Write once only

MUXCR0

Reset value: 0000 0000 (00h)

654

MIR[7:0]

Read / Write once only

Table 13.

MUXCRx register description

Bit

Name

Function

15:0 MIR[15:0]

This 16-bit register is read/write by software but can be written only once between

two reset events. It is cleared by hardware after a reset. When both MUXCR0 and

MUXCR1 registers are at 00h, the multiplexed PA3/RESET pin acts as RESET. To

configure this pin as output (Port A3), write 55h to MUXCR0 and AAh to MUXCR1.

These registers are one-time writable only.

– To configure PA3 as general purpose output:

After power-on / reset, the application program has to configure the I/O port by

writing to these registers as described above. Once the pin is configured as an

I/O output, it cannot be changed back to a reset pin by the application code.

– To configure PA3 as RESET:

An internally generated reset (such as POR, LVD, WDG, illegal opcode) will clear

the two registers and the pin will act again as a reset function. Otherwise, a

power-down is required to put the pin back in reset configuration.

Table 14.

Multiplexed I/O register map and reset values

Address (Hex.)

76543210

0047h

MUXCR0

Reset value

MIR7

MIR6

MIR5

MIR4

MIR3

MIR2

MIR1

MIR0

0048h

MUXCR1

Reset value

MIR15

MIR14

MIR13

MIR12

MIR11

MIR10

MIR9

MIR8

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