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ST7LUS5 数据表(PDF) 49 Page - STMicroelectronics |
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ST7LUS5 数据表(HTML) 49 Page - STMicroelectronics |
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49 / 124 page ![]() ST7LUS5, ST7LU05, ST7LU09 Power saving modes 49/124 The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 14.1 on page 114 for more details). Figure 21. HALT timing overview 1. A reset pulse of at least 42µs must be applied when exiting from Halt mode. HALT RUN RUN 64 CPU CYCLE DELAY RESET(1) OR INTERRUPT HALT INSTRUCTION FETCH VECTOR [Active Halt disabled] |
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