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ST7LUS5 数据表(PDF) 98 Page - STMicroelectronics |
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ST7LUS5 数据表(HTML) 98 Page - STMicroelectronics |
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98 / 124 page ![]() Electrical characteristics ST7LUS5, ST7LU05, ST7LU09 98/124 Figure 43. Typical IDD in Slow Wait mode vs. fCPU Figure 44. Typical IDD vs. temperature at VDD = 5 V and fCPU = 8 MHz 12.5 Clock and timing characteristics Subject to general operating conditions for VDD, fOSC, and TA. Table 69. On-chip peripherals Symbol Parameter Conditions Typ(1) 1. Not tested in production, guaranteed by characterization Unit IDD(AT) 12-bit auto-reload timer supply current(2) 2. Data based on a differential IDD measurement between reset configuration (timer stopped) and the timer running in PWM mode at fCPU = 8 MHz fCPU = 8 MHz VDD = 5.0V 30 µA IDD(ADC) ADC supply current when converting (3) 3. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with amplifier off fADC = 4 MHz VDD = 5.0V 750 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 Vdd [V] 2MHz 4MHZ 8MHz 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 -45 25 90 Vdd [V] RUN WAIT SLOW SLOWWAIT |
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