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ST7LUS5 数据表(PDF) 65 Page - STMicroelectronics |
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ST7LUS5 数据表(HTML) 65 Page - STMicroelectronics |
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65 / 124 page  ST7LUS5, ST7LU05, ST7LU09 On-chip peripherals 65/124 Input capture The 8-bit input capture register is used to latch the free-running up counter after a rising or falling edge is detected on the LTIC pin. When an input capture occurs, the ICF bit is set and the LTICR register contains the MSB of the free-running up counter. An interrupt is generated if the ICIE bit is set. The ICF bit is cleared by reading the LTICR register. The LTICR is a read only register and always contains the data from the last input capture. Input capture is inhibited if the ICF bit is set. 10.1.4 Low power modes 10.1.5 Interrupts Note: The TBF and ICF interrupt events are connected to separate interrupt vectors (see Chapter 7: Interrupts). They generate an interrupt if the enable bit is set in the LTCSR register and the interrupt mask in the CC register is reset (RIM instruction). Figure 30. Input capture timing diagram Table 33. Effect of low power modes on Lite timer Mode Description Wait No effect on Lite timer Active Halt Halt Lite timer stops counting Table 34. Lite timer interrupt control/wake-up capability Interrupt event Event flag Enable control bit Exit from Wait Exit from Halt Exit from Active Halt Timebase event TBF TBIE Yes No Yes IC event ICF ICIE No 0004h 13-bit COUNTER t 0001h fOSC xxh 0002h 0003h 0005h 0006h 0007h 04h LTIC PIN ICF FLAG LTICR REGISTER CLEARED 125ns (@ 8 MHz fOSC) fCPU BY S/W 07h READING LTIC REGISTER |
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