ST7LUS5 datasheet(72/124 Pages) STMICROELECTRONICS

72 / 124 page

On-chip peripherals

ST7LUS5, ST7LU05, ST7LU09

72/124

Counter register high (CNTRH)

Counter register low (CNTRL)

1OVFIE

Overflow Interrupt Enable

This bit is read/write by software and cleared by hardware after a reset.

0: OVF interrupt disabled

1: OVF interrupt enabled

0CMPIE

Compare Interrupt Enable

This bit is read/write by software and cleared by hardware after a reset. It is used

to mask the interrupt generation when CMPF bit is set.

0: CMPF interrupt disabled

1: CMPF interrupt enabled

CNTRH

Reset value: 0000 0000 (00h)

Reserved

CNTR11

CNTR10

CNTR9

CNTR8

RORORO

CNTRL

Reset value: 0000 0000 (00h)

654

CNTR7

CNTR6

CNTR5

CNTR4

CNTR3

CNTR2

CNTR1

CNTR0

Table 41.

CNTH High and Low counter descriptions

Bits

Name

Function

15:12

Reserved, must be kept cleared.

11:0

CNTR[11:0]

Counter Value

This 12-bit register is read by software and cleared by hardware after a reset.

The counter is incremented continuously as soon as a counter clock is

selected. To obtain the 12-bit value, software should read the counter value in

two consecutive read operations. As there is no latch, it is recommended to

read LSB first. In this case, CNTRH can be incremented between the two read

operations. To have an accurate result when fCOUNTER =fCPU, special care

must be taken when CNTRL values close to FFh are read.

When a counter overflow occurs, the counter restarts from the value specified

in the ATR register.

Table 40.

ATCSR register description

Bit

Name

Function

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