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ST7LUS5 数据表(PDF) 79 Page - STMicroelectronics |
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ST7LUS5 数据表(HTML) 79 Page - STMicroelectronics |
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79 / 124 page  ST7LUS5, ST7LU05, ST7LU09 On-chip peripherals 79/124 Data register high (ADCDRH) Data register low (ADCDRL) 2:0 CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert as follows: 000: Channel pin = AIN0 001: Channel pin = AIN1 010: Channel pin = AIN2 011: Channel pin = AIN3 100: Channel pin = AIN4 Note: A write to the ADCCSR register (with ADON set) aborts the current conversion, resets the EOC bit and starts a new conversion. ADCDRH Reset value: 0000 0000 (00h) 7 654 32 10 D[9:2] RO Table 49. ADCDRH register description Bit Name Function 7:0 D[9:2] MSB of Analog Converted Value ADCDRL Reset value: 0000 0000 (00h) 7 654 32 10 Reserved SLOW Reserved D[1:0] - R/W - R/W Table 50. ADCDRL register description Bit Name Function 7:4 - Reserved, forced by hardware to 0 3SLOW Slow mode This bit is set and cleared by software. It is used together with the SPEED bit in the ADCCSR register to configure the ADC clock speed as shown in Table 51. 2 - Reserved, forced by hardware to 0 1:0 D[1:0] LSB of Analog Converted Value Table 48. ADCCSR register description (continued) Bit Name Function |
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