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数据搜索系统，热门电子元器件搜索 |
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ST7LUS5 数据表(PDF) 17 Page - STMicroelectronics |
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ST7LUS5 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 124 page  ST7LUS5, ST7LU05, ST7LU09 Register and memory map 17/124 004Bh 004Ch 004Dh 004Eh 004Fh 0050h DM(4) DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W 0051h to 007Fh Reserved area (47 bytes) 1. x = undefined, R/W = read/write 2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 3. The bits associated with unavailable pins must always keep their reset value. 4. For a description of the DM registers, see the ST7 ICC Protocol Reference Manual. Table 3. Hardware register map(1) (continued) Address Block Register label Register name Reset status Remarks |
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