ST7LUS5 datasheet(110/124 Pages) STMICROELECTRONICS

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Electrical characteristics

ST7LUS5, ST7LU05, ST7LU09

110/124

12.10

10-bit ADC characteristics

Figure 58.

Typical application with ADC

Table 82.

10-bit ADC characteristics(1)

Symbol

Parameter

Conditions

Min

Typ(2)

Max

Unit

fADC

ADC clock frequency

MHz

VAIN

Conversion voltage range(3)

VSSA

VDDA

RAIN

External input resistor

VDD = 5V, fADC =4 MHz

8k(4)

Ω

VDD = 3.3V, fADC =4MHz

7k(4)

CADC

Internal sample and hold capacitor

tSTAB

Stabilization time after ADC enable

fCPU = 8 MHz, fADC = 4 MHz

0(5)

µs

tADC

Conversion time (Sample+Hold)

3.5

Sample capacitor loading time

1/fADC

Hold conversion time

Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.

Unless otherwise specified, typical data are based on TA = 25°C and VDD -VSS = 5V. They are given only as design

guidelines and are not tested.

When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.

Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

Ω). Data

based on characterization results, not tested in production.

The stabilization time of the A/D converter is masked by the first tLOAD. The first conversion after the enable is then always

valid.

AINx

ST7LUxx

VDD

±1µA

0.6V

CADC

VAIN

RAIN

10-bit A/D

Conversion

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