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R5F104FCAFP 数据表(PDF) 105 Page - Renesas Technology Corp

部件名 R5F104FCAFP
功能描述  True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz
PDF  207 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F104FCAFP 数据表(HTML) 105 Page - Renesas Technology Corp

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RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
R01DS0131EJ0350 Rev.3.50
105 of 200
Jun 30, 2020
2.5.2 Serial interface IICA
(1) I2C standard mode
(TA = –40 to +85°C, 1.6 V
≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
SCLA0 clock frequency
fSCL
Standard mode:
fCLK
≥ 1 MHz
2.7 V
≤ EVDD0 ≤ 5.5 V
0
100
0
100
0
100
kHz
1.8 V
≤ EVDD0 ≤ 5.5 V
0
100
0
100
0
100
kHz
1.7 V
≤ EVDD0 ≤ 5.5 V
0
100
0
100
0
100
kHz
1.6 V
≤ EVDD0 ≤ 5.5 V
–
0
100
0
100
kHz
Setup time of restart
condition
tSU:STA
2.7 V
≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.7 V
≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.6 V
≤ EVDD0 ≤ 5.5 V
–
4.7
4.7
µs
Hold timeNote 1
tHD:STA
2.7 V
≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.7 V
≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.6 V
≤ EVDD0 ≤ 5.5 V
–
4.0
4.0
µs
Hold time when SCLA0 =
“L”
tLOW
2.7 V
≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.7 V
≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.6 V
≤ EVDD0 ≤ 5.5 V
–
4.7
4.7
µs
Hold time when SCLA0 =
“H”
tHIGH
2.7 V
≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.7 V
≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.6 V
≤ EVDD0 ≤ 5.5 V
–
4.0
4.0
µs
Data setup time
(reception)
tSU:DAT
2.7 V
≤ EVDD0 ≤ 5.5 V
250
250
250
ns
1.8 V
≤ EVDD0 ≤ 5.5 V
250
250
250
ns
1.7 V
≤ EVDD0 ≤ 5.5 V
250
250
250
ns
1.6 V
≤ EVDD0 ≤ 5.5 V
–
250
250
ns
Data hold time
(transmission)Note 2
tHD:DAT
2.7 V
≤ EVDD0 ≤ 5.5 V
0
3.45
0
3.45
0
3.45
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
0
3.45
0
3.45
0
3.45
µs
1.7 V
≤ EVDD0 ≤ 5.5 V
0
3.45
0
3.45
0
3.45
µs
1.6 V
≤ EVDD0 ≤ 5.5 V
–
0
3.45
0
3.45
µs
Setup time of stop
condition
tSU:STO
2.7 V
≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.7 V
≤ EVDD0 ≤ 5.5 V
4.0
4.0
4.0
µs
1.6 V
≤ EVDD0 ≤ 5.5 V
–
4.0
4.0
µs
Bus-free time
tBUF
2.7 V
≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.7 V
≤ EVDD0 ≤ 5.5 V
4.7
4.7
4.7
µs
1.6 V
≤ EVDD0 ≤ 5.5 V
–
4.7
4.7
µs
(Notes, Caution and Remark are listed on the next page.)



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