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R5F104FCAFP 数据表(PDF) 107 Page - Renesas Technology Corp

部件名 R5F104FCAFP
功能描述  True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz
PDF  207 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F104FCAFP 数据表(HTML) 107 Page - Renesas Technology Corp

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RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
R01DS0131EJ0350 Rev.3.50
107 of 200
Jun 30, 2020
(2) I2C fast mode
(TA = –40 to +85°C, 1.6 V
≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
SCLA0 clock frequency
fSCL
Fast mode:
fCLK
≥ 3.5 MHz
2.7 V
≤ EVDD0 ≤ 5.5 V
0
400
0
400
0
400
kHz
1.8 V
≤ EVDD0 ≤ 5.5 V
0
400
0
400
0
400
kHz
Setup time of restart
condition
tSU:STA
2.7 V
≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
Hold timeNote 1
tHD:STA
2.7 V
≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
Hold time when SCLA0 =
“L”
tLOW
2.7 V
≤ EVDD0 ≤ 5.5 V
1.3
1.3
1.3
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
1.3
1.3
1.3
µs
Hold time when SCLA0 =
“H”
tHIGH
2.7 V
≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
Data setup time
(reception)
tSU:DAT
2.7 V
≤ EVDD0 ≤ 5.5 V
100
100
100
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
100
100
100
µs
Data hold time
(transmission)Note 2
tHD:DAT
2.7 V
≤ EVDD0 ≤ 5.5 V
0
0.9
0
0.9
0
0.9
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
0
0.9
0
0.9
0
0.9
µs
Setup time of stop
condition
tSU:STO
2.7 V
≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
0.6
0.6
0.6
µs
Bus-free time
tBUF
2.7 V
≤ EVDD0 ≤ 5.5 V
1.3
1.3
1.3
µs
1.8 V
≤ EVDD0 ≤ 5.5 V
1.3
1.3
1.3
µs
Notes 1.
The first clock pulse is generated after this period when the start/restart condition is detected.
2.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution
The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Fast mode:
Cb = 320 pF, Rb = 1.1 k
Ω



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