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R5F104FCAFP 数据表(PDF) 108 Page - Renesas Technology Corp |
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R5F104FCAFP 数据表(HTML) 108 Page - Renesas Technology Corp |
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108 / 207 page ![]() RL78/G13 2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C) R01DS0131EJ0350 Rev.3.50 108 of 200 Jun 30, 2020 (3) I2C fast mode plus (TA = –40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode Unit MIN. MAX. MIN. MAX. MIN. MAX. SCLA0 clock frequency fSCL Fast mode plus: fCLK ≥ 10 MHz 2.7 V ≤ EVDD0 ≤ 5.5 V 0 1000 – – kHz Setup time of restart condition tSU:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 – – µs Hold timeNote 1 tHD:STA 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 – – µs Hold time when SCLA0 = “L” tLOW 2.7 V ≤ EVDD0 ≤ 5.5 V 0.5 – – µs Hold time when SCLA0 = “H” tHIGH 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 – – µs Data setup time (reception) tSU:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 50 – – µs Data hold time (transmission)Note 2 tHD:DAT 2.7 V ≤ EVDD0 ≤ 5.5 V 0 0.45 – – µs Setup time of stop condition tSU:STO 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 – – µs Bus-free time tBUF 2.7 V ≤ EVDD0 ≤ 5.5 V 0.5 – – µs Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. 2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect destination. Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Fast mode plus: Cb = 120 pF, Rb = 1.1 k Ω IICA serial transfer timing tLOW tR tBUF tHIGH tF tHD:STA Stop condition Start condition Restart condition Stop condition tSU:DAT tSU:STA tSU:STO tHD:STA tHD:DAT SCLAn SDAAn Remark n = 0, 1 |
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